A Top-Level View of Computer Function and Interconnection
Computer Components
I think this figure describes enough.
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Ref: Computer Organization and Architecture 5th edition,
William Stallings, P.91
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Computer Function
The basic function performed by a computer is execution
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Ref: Computer Organization and Architecture 5th edition,
William Stallings, P.92
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Terms
- Fetch: copy data from memory
to
- At the beginning of each instruction cycle the processor fetches an instruction from memory
- The program counter (PC) holds the address of the instruction to be fetched next
- The processor increments the PC after each IR - Execute:
- The processor interprets the instruction and performs the required action - Opcode: operation code some part of instruction. It refers which operation has to do
- Operand: remainder part of instruction. It refers address
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Ref: Computer Organization and Architecture 5th edition,
William Stallings, P.93
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Example of program fetches and execution
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Ref: Computer Organization and Architecture 5th edition,
William Stallings, P.93
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Interrupts
Virtually all computers provide a mechanism by which other modules (I/O, memory) may interrupt the normal processing of the processor. (I will almost skip this part)
- Interrupt priority
Interrupt service routine (ISR) → PC ← ISR (to get start address)
Interrupt Service Routine I( ) - Context Switching
If certain currently processed job is interrupted, it's information (PC, Accumulator, Registers, SP: stack pointer, etc.) would be stored in memory. Then, process next (which makes interrupt) job → execution → restore interrupted process.
Class of Interrupt
- Program
- Arithmetic overflow
- Division by zero
- Attempt execute all illegal machine instruction
- Reference outside a user's allowed memory space
- Timer
- I/O
- Hardware failure (Ex. Parity error)
It just checks odd # bit changes in the system → part of the error checking process
Interconnection Structure
DMA (Direct Memory Access)
DMA moves very simple. DMA process very simple works (Ex. Data copying) without CPU overhead. So, it increases efficiency. If DMA under processing, CPU could not access that devices.
If several devices request some process at the same time, bus arbiter start process.
Terms
Arbitration: Because only one unit at a time can successfully transmit over the bus, the arbiter is responsible for allocating time on the bus.
Bus Interconnection
Bus structure
- Data Bus
- Data lines that provide a path for moving data among system
- May consist of 32, 64, 128, or more separate lines → combined with word size - Address Bus
- Used to designate the source or destination of the data on the data bus
- Desired word on the address lines
- Width determines the maximum possible memory capacity of the system - Control Bus
- Used to control the access and the use of the data and address lines
Ex. Address width = 34bit
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Ref: Computer Organization and Architecture 5th edition,
William Stallings, P.108
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Synchronous / Asynchronous Bus operation
Timing refers to the way in which events are coordinated on the bus. Buses to use either synchronous timing or asynchronous timing.
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Ref: Computer Organization and Architecture 5th edition,
William Stallings, P.113
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Figure 3.18 shows how to process I/O between memory and CPU. At t1, the CPU sends address to check. At t2, it can work two different ways. One is read from the data. Another one writes to data. I think below figure is looking better.
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| Read/Write operation |
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| How to get I/O data |
IO mapped I/O & Memory mapped I/O
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| Memory mapped & I/O mapped |
Calculating memory space and word
Ex. 32bit processor → 32bit = 4byte = 1word
64bit processor → 64bit = 8 bytes = 1word
Ex. 1GB D-Ram
2^30 (B) = 1G (B)
Number of addresses 8 pins for data (memory architecture problem)
If you need more example about real processor Click here.
If you need more example about real processor Click here.
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